Non-volatile memory systems, such as flash memory, have been widely adopted for use in host devices, such as consumer products. Flash memory may be found in different forms, such as in the form of a portable memory card that can be carried between host devices or as a solid state disk (SSD) embedded in a host device.
The flash memory may be composed of memory cells. The memory cells may be operated to store two levels of charge so that a single bit of data is stored in each cell. This is typically referred to as a binary or single level cell (SLC) memory. Alternatively, the memory cells may be operated to store more than two detectable levels of charge in each charge storage element or region, thereby to store more than one bit of data in each. This latter configuration is referred to as multi-level cell (MLC) memory.
For example, an MLC memory cell can include four possible states per cell, thereby storing two bits of information per cell. In this way, there are multiple states per cell, with bit values corresponding to each of the states, such as “00”, “01”, “10”, and “11”. The MLC memory cell may experience state widening, resulting in potential errors. For example, the “A” state (bit value “00”) may experience state widening, resulting in an increased error rate for the MLC cells.
One solution to combat state widening is conducting high voltage stress of the wordlines. In particular, wordline-to-wordline stress routines may be implemented in which the wordlines are stressed with high voltage during an erase cycle. However, the wordline stress routines, while solving one problem, may create another. High voltage stress may cause data retention problems in which charge leaks out of the memory cell. Accordingly, a need exists to combat state widening while avoiding data retention problems.